I/O Permutations (2D Case) - I/O Permutations (2D Case) - 2026.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-06-23
Version
2026.1 English

The following figure illustrates how to compute the I/O permutations required for a 2D PFA solution. The input permutation relies on a simple modulo computation with the relatively prime factors \(N_1\) and \(N_2\). The figure gives a specific sample with \(N_1=3% and \)N_2=5\(. The input index mapping can be written in a 2D matrix form, or as a 1D address permutation \)P_i$.

The output permutation mapping relies on a similar modulo computation but with factors \(K_3\) and \(K_4\) computed from \(N_1\) and \(N_2\) and their “multiplicative modulo inverses”. Such an inverse \(\{(a^{-1}\})_N\equiv I\) is defined such that \(mod\{(a\times I,N\})=1\). Using this to solve for \(\{(N_2^{-1}\})\_{N_1}\) and \(\{(N_1^{-1}\})\_{N_2}\) yields the solution of \(K_3=10\) and \(K_4=6\) shown in the figure. Once again, the output index mapping can be written in a 2D matrix form, or as a 1D address permutation \(P_o\).

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