You create the platform using the Versal extensible platform configurable example design (CED) included in AMD Vivado™.
In this example, you add custom IPs to the block design. The first one, AXI4S_Counter is a counter that generates data on a 64-bit AXI4-Stream interface. The second one, dummy Sink, is an AXI4-Stream slave that accepts any data and drops it (tready is always High). The AXI4-Stream interfaces of these two IP blcoks do not connect to any slave or master interfaces. You connect them to the AI Engine using the V++ linker.
Note: The AI Engine expects AXI4-Stream-compliant interfaces connected to its AXI4-Stream interfaces. Although the following guide focuses on designing Video IPs, it also contains considerations useful for designing any AXI4-Stream IP.
For the V++ linker to detect the two AXI4-Stream interfaces, add them to the platform properties. Assign each a unique SP tag.
Use the following Tcl commands:
set_property PFM.AXIS_PORT {M00_AXIS {type "M_AXIS" sptag "master_axi_1" is_range "false"}} [get_bd_cells /AXI4S_Counter_0]
set_property PFM.AXIS_PORT {S00_AXIS {type "S_AXIS" sptag "slave_axi_1" is_range "false"}} [get_bd_cells /dummy_sink_0]
Or you can do this through the Vivado GUI using the Platform tab.
Note: The preceding flow assumes that the RTL AXI4-Stream interfaces are part of the block design (BD). In some designs, the RTL exists outside the BD. In that case, you can simply add an interface port to the BD set as AXI4-Stream (xilinx.com:interface:axis_rtl:1.0). Then add an IP in the BD to pass through all interface nets. The option appears in the Part 2.
You can generate the Vivado Platform with the following make command:
make vivado_platform
The Vivado project generates under Vivado/build/custom_pfm_strmIn_strmOut.