HLS PL Kernels - HLS PL Kernels - 2025.2 English - XD100

After coming up with 400 tile AI Engine design, the next step is to move data from DDR and send it to the AI Engine. Use the AMD Vitis™ core development kit to create kernel code in C++ for FPGA acceleration. The Vitis Compiler (v++ -c) compiles the kernel code into kernel objects (XO). The following table describes each HLS PL kernel.

Kernel Name	Description	Fmax
mm2s_mp	Dual-channel data-mover that moves data from DDR to AXI4-Stream.	411 MHz
packet_sender	Packet switching kernel that packetizes AXI4-Stream data by generating a header packet and appropriately asserting TLAST	580 MHz
packet_receiver	Packet switching kernel that evaluates packet headers from incoming streams and reroutes data to one of 4 AXI4-Streams	499.5 MHz
s2mm_mp	Quad-channel data-mover that moves data from AXI4-Stream to DDR.	411 MHz

Using Vivado timing closure techniques, you can increase the FMax if needed. To showcase the example, integrate using the 300 MHz clock. There is also a 400 MHz timing-closed design in the beamforming tutorial.