Graph and Kernel Code - Graph and Kernel Code - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English
  1. Run the following make command to compile the design:

    make aie
    
  2. Open the compile result in an AMD Vitis™ Analyzer. You can find it in the following directory:

    vitis_analyzer Work/graph.aiecompile_summary
    
  3. Examine the graph view in Vitis Analyzer.

    Graph View

The design contains two kernels, aie_dest1 and aie_dest2. A stream connection and a buffer connection (ping-pong buffers buf1 and buf1d) connect these two kernels. The stream connection contains two stream switch FIFOs, Fifo0(24,0) and Fifo1(24,0). These dedicated FIFOs reside in the stream switch of AI Engine array tile 24_0. The design inserts these FIFOs to prevent deadlock (refer to AI Engine Hang Analysis).

The input from the PL connects to the ping-pong buffers buf0 and buf0d, which kernel aie_dest1 reads. Kernel aie_dest2 connects its output to the PL through a stream connection.

The code for aie_dest1 is as follows:

using namespace adf;
__attribute__ ((noinline)) void aie_dest1(input_buffer<int32,extents<32>> &in, 
       output_stream<int32> *out, output_buffer<int32,extents<32>> &outm){
	auto inIter=aie::begin_vector<4>(in);
	auto outmIter=aie::begin_vector<4>(outm);
	aie::vector<int32,4> tmp;
	for(int i=0;i<8;i++)
	chess_prepare_for_pipelining
	{
		tmp=*inIter++;
		writeincr(out,tmp);
		*outmIter++=tmp;
	}
}

It reads 32 int values from the input buffer and writes them to the stream and buffer output. The __attribute__ ((noinline)) command instructs the tool the keep the hierarchy of the kernel function.

The code for aie_dest2 is as follows:

using namespace adf;
__attribute__ ((noinline)) void aie_dest2(input_stream<int32> *in, input_buffer<int32,extents<32>> &inm, 
       output_stream<int32> *outm){
	auto inmIter=aie::begin_vector<4>(inm);
	aie::vector<int32,4> tmp;
	aie::vector<int32,4> tmp2;
	for(int i=0;i<8;i++)
	chess_prepare_for_pipelining
	{
		tmp=readincr_v<4>(in);
		tmp2=*inmIter++;
		writeincr(outm,tmp+tmp2);
	}
}

It reads from the stream input and the buffer, and writes to the stream output.