Fixed-Point Pipeline - Fixed-Point Pipeline - 2026.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document_ID
XD100
Release_Date
2026-07-20
Version
2026.1 English

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In this pipeline, you can see the data selection and shuffling units: PMXL, PMXR, and PMC. The pre-add (PRA) is before the multiply block. Two lane reduction blocks (PSA, PSB) allow performing up to 128 multiplies and getting an output on 16 lanes down to two lanes. The accumulator block is fed either by its own output (AM) or by the upshift output. The feedback on the ACC block is only one clock cycle.