In this design the first kernel in the dataflow is the down-converter 5/7 followed by the up-converter.
make VERSION=2 clean buffer aie aiesim aieviz
The compiler decides that for each iteration it runs seven times the down-converter and five times the up-converter.
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INFO: [aiecompiler 77-5917] Repetition count for G.G2.k1 is 7.
INFO: [aiecompiler 77-5917] Repetition count for G.G2.k2 is 5.
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You can run the simulation and visualize the result:
make aiesim aieviz
The four iterations (28 runs of the down-converter and 20 runs of the up-converter) take approximately 14 µs.
Input and output have the same throughput. The simulator output shows this:
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Port Name | Type | Average Throughput
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input64_1 | IN | 4973.135738 MBps
output64_1 | OUT | 4943.565168 MBps
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The throughput is higher than the previous situation because between the two kernels the throughput is much less so the processing is much faster. The result is a much higher throughput at the I/O ports of the design.