TDM FIR uses 32 AI Engine tiles, leveraging newly introduced Vitis Library packet switching IP.
The 4k-pt IFFT is implemented using 2D architecture (with Mode 1), with resources split between:
16 AI Engine tiles (compute)
Seven memory tiles (front transpose and back transpose)
PL (middle transpose)
From a bandwidth perspective, the design requires two input and four output streams.
Custom HLS blocks (packet_sender and packet_receiver) interface with AI Engine packet switching IP.
Output ports of AI Engine going to PL can arrive at different times causing minor throughput loss. You can compensate by adding FIFOs during the v++ linking step Specifying-Streaming-Connections.