Each PL kernel has run_<kernel_name>.tcl, bd_<kernel_name>.tcl, kernel_<kernel_name>.xml, and hdl/*.v RTL code as dependencies.
| Filename | Description |
|---|---|
| bd_\<kernel_name>.tcl | The Tcl script that creates the block design in the Vivado project. |
| kernel_\<kernel_name>.xml | The XML file that specifies the ports and defines the PL kernel. |
The hdl/ folder in each PL kernel folder contains the Verilog RTL that is used to create the PL kernels.