Debug Methodologies - 2024.2 English - XD100

X86 Simulation - Vitis IDE Flow
Build and Simulate in the Vitis IDE	Demonstrates how to use the Vitis IDE to build and simulate the AI Engine design.
Debug Using printf()	Demonstrates how to add the formatted `printf()` to print debug messages.
Debug Using printf() with Vector Data Types	Demonstrates how to print the vector output data value via `printf()`.
Debug Using the Vitis IDE Debugger	Demonstrates how to use the Vitis IDE debugger to debug an AI Engine design.
x86simulator Options for Debugging	Demonstrates how to use the x86simulator options file for debugging.
Data Dump	Demonstrates how to use the data dump feature with a practical scenario.
Deadlock Detection	Demonstrates how to debug deadlock scenarios in an x86simulation.
Trace Report in the File	Demonstrates how to visualize the trace report in the file.
Trace Report in the Output Console	Demonstrates how to visualize the trace report in the output console during runtime.
Memory Access Violation and Valgrind Support	Demonstrates how to debug memory access violations in an AI Enigne design using Valgrind support.
Using the GDB in the Command Line	Demonstrates debugging in command line using the GNU Debugger (GDB).
x86simulation on the Command Line	Demonstrates how to run x86simulation on the command line.
x86simulation with the GDB	Demonstrates how to use the GDB during x86simulation.
x86simulator Using a GDB Server	Demonstrates how to use a GDB server to debug the design.
AIE Simulation - Vitis IDE Flow
Build and Simulate in the Vitis IDE	Demonstrates how to use the Vitis IDE to build and simulate an AI Engine design.
Debug Using printf	Explains how to add a `printf()` statement, and view the output in the console.
Debug Using the Vitis IDE Debugger	Explores different debugging techniques that use the Vitis IDE debugger.
Enabling Profile and Trace Options	Explains how to enable profile and trace options in the Vitis IDE. Explores different event trace dump options like VCD and WDB.
Deadlock Detection	Shows a practical deadlock scenario and some simulator options to identify the deadlock.
Visualizing Deadlock in the Vitis Analyzer	Explains how to visualize deadlock using trace information in the Vitis Analyzer, and identify the root cause.
Debugging Memory Access Violations	Introduces an out of bound read access, and explains how to identify the violations using AI Engine simulator options.
Single Kernel Debug	Explains how to debug a single kernel design usign a pipeline view in the Vitis IDE.
Design Performance Debug	Shows how to calculate kernel latency and throughput using profile information.
Hardware Emulation - Vitis IDE Flow
Build for Hardware Emulation Using the Vitis IDE	Explains how to create a system project, build for hardware emulation, and run.
Debug PL Kernels Using the Vivado Logic Simulator	Explains how to use the AMD Vivado™ XSIM to debug the PL kernels.
Performance of the AI Engine Using Hardware Emulation Results	This section profiles the system for hardware emulation and compares the throughput of the AI Engine design in hardware emulation with the throughput in a AI Engine simulation.
Command Line Project Source Code Debug with the Vitis IDE	This section helps you debug your command line project using the features of the Vitis IDE debugger without porting your system design to the IDE.
Hardware - Command Line Flow
Running the Design on Hardware	Explains how to determine the functional correctness of the design by running on hardware.
Error Handling and Reporting in the Host Application	Explains how to use error reporting APIs to handle errors in the host code.       * XRT error handling APIs - This method reports errors that can be detected during the XRT runtime function call or underneath driver, system, hardware, etc.       * Using XBUtil - XButil error reporting can accumulate all the errors from various classes and sorts them by timestamp.
Analyzing Run Results	Explains different techniques (XRT, XBUtil, and XSDB) to analyze the design by running on hardware and helps to choose from the following methodologies.       - AI Engine status using XRT - Using XRT is fast and host executable can automatically reads the `xrt.ini` file to configure the runtime. -       * Manual AI Engine status using XBUtil utility - XBUtil is a standalone command utility included with XRT and does not require any special file to handle. You can directly use XBUtil commands on the console after boot.       - Deadlock detection using XSDB - XSDB runs independent of XRT and can analyze the results before, during, or after design runs. Also, you can use the XSDB for baremetal applications in addition to the Linux-based applications.
Using APIs in the Host Application	Explains how to modify the host code to add APIs in the host application that helps profiling the design for getting throughput, latency, and bandwidth.       - Profiling Graph throughput - Provides insight on how to modify the host code for profiling the number of samples sent and received.       * Profiling to count Samples sent and received (Exercise Step) - Provides insight on how to modify the host code for profiling the number of samples sent and received.
Hardware Profiling Feature - XRT Flow	Explains how to set up the configuration file `xrt.ini`, and run the hardware design to generate profile data using the XRT flow.       - Open multiple profile runs in Vitis Analyzer - This exercise helps you understand how to open different profile summaries (two different runs) in a single Vitis Analyzer view.       - Profiling Data Explaination - This explains how to analyze AI Engine core,memory and interface profiling data. Also discusses what action should be taken based on the stall time and DMA lock time.
Hardware Profiling Feature - XSDB Flow	This method explains how to use the XSDB-based flow to profile for both baremetal and Linux operating systems.
Profiling Using PL Profile Monitors	Explains how to insert PL profile monitors in the v++link command. This helps identify specific PL kernels(s) causing a performance drop.
Inserting ILA(s) to Monitor Specific AXI Interfaces	Explains how to insert one or more integrated logic analyzers (ILAs) to monitor specific PL AXI interfaces to help identify exactly where and when a throughput drop occurs. Also helps in identifying whether data is sent correctly to the AI Engine from the PL compenents and received correctly from the AI Engine to the PL.
Build the Design for Event Trace Analysis	Explains how to use different event trace options for compiling and its significance. Also walks through the steps to generate the hardware image.       - Prepare for the hardware run.
Event Trace Analysis - XRT Flow	Explains how to do an AI Engine event trace and analysis by setting up the configuration file `xrt.ini` and run the hardware design to generate trace data using the XRT flow.       * Launch Vitis Analyzer to Examine Event Trace Files       - Details of the Event Trace data
Event Trace Analysis - XSDB Flow	This method explains how to use the XSDB-based flow to perform event trace analysis on an AI Engine design.
Event Trace Considerations	This method explains how to use the XSDB-based flow to perform event trace analysis on anAI Engine design.       - Event Trace Choice Considerations       - Number of Event Trace Streams Methodology       - Event Trace Limitations
Debug the Host/Kernel Source Code Using the Vitis IDE	Explains how to set up the target connection for hardware in the Vitis IDE and debug the host code and kernel source code in the Vitis IDE debugger.