The data register is limited to 1024 bits (v32cint16). The maximum bitwidth of the coefficient register is 512 bits (v16cint16). With a streaming interface (single stream to start with), the system can read four cint16 in one instruction, but it takes four clock cycles to perform the same operation again. Reading four samples at a time allows the use of mul4 and mac4 intrinsics.
Not all intrinsics exist for the AI Engine. Only two intrinsics handle four lanes for complex 16 bits x complex 16 bits:
This tutorial assumes finite length loops (by default 512 input/output samples) for ease of debugging. You can increase or decrease the number of iterations up to infinite loops (while(1) { ...}). The filter delay-line must preserve its status between kernel calls. A 32-tap filter requires at least 31 delay-line samples. Because 32 samples fit in a Y register, this tutorial uses a v32cint16 variable to maintain this delay-line. The kernel call loads this delay-line from memory at the beginning and stores it back at the end. The coefficients require v8cint16 with no other options.
A mul4 operating on cint16 x cint16 can perform eight operations in one clock cycle, leading to two operations per lane.