Conclusion - 2025.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2025-08-25
Version
2025.1 English

This tutorial has shown how to use the tiling parameter to access the memory modules in a more complex way than a simple read/write access. It is possible to define a complex access pattern using tiling parameters at the output of the source kernel and at the input of the destination kernel. The aiecompiler will automatically insert the necessary stream communication between the 2 kernels.

The tensor buffer stream is a powerful tool to access the buffer in a more complex way from withinthe kernel itself. It is possible to define a multi-dimensional access scheme and to read the buffer in a stream way but with complex address generation under the hood.