Based on the specified sampling rate and Figure 2, you need to perform 19 MACs every cycle where each MAC operation involves a cint16 data with a int16 coefficient.
Based on the specified data and coefficient types, you should be able to perform 16 cint16 x int16 MACs every cycle in a single tile, as described in Table 1 of the Versal Adaptive SoC AI Engine Architecture Manual (AM009).