The following table compares the implementation of a farrow filter in AIE and AIE-ML architectures. This indicates that approximately twice the number of tiles is required for kernel computation in AIE_ML compared to the AIE architecture to achieve the same performance. | Design | Tiles for AIE Kernels | Tiles for Buffers | Total Tiles | Throughput | Relative MSPS per tile | |————————|———————–|——————-|————-|———————|————————| | farrow - AIE (PLIO) | 2 | 5 | 5 | 1138 MSPS (HW_EMU) | 227.6 | | farrow - AIE-ML (GMIO) | 5 | 9 | 9 | 1061 MSPS (HW_EMU) | 124.8 |
* Total Tiles: Represents the total count of tiles, including those that have both kernels and buffers within the same tile.