The following table compares the farrow filter implementation across AIE, AIE-ML, and AIE-ML v2 architectures. Notice that AIE-ML v2 requires about twice the tiles for kernel computation compared to AIE. It needs two more tiles than AIE-ML architecture, yet delivers almost twice the performance.
Design |
Tiles for AIE Kernels |
Tiles for Buffers |
Total Tiles |
Throughput |
Relative MSPS per tile |
|---|---|---|---|---|---|
farrow - AIE (PLIO) |
2 |
5 |
5 |
1135 MSPS (HW_EMU) |
227.6 |
farrow - AIE-ML (GMIO) |
5 |
8 |
8 |
1052 MSPS (HW_EMU) |
131.5 |
farrow - AIE-MLv2 (GMIO) |
5 |
10 |
10 |
1947 MSPS (HW_EMU) |
194.7 |
* Total Tiles: Represents the total count of tiles, including those that have both kernels and buffers within the same tile.