Channelizers today can operate at sampling rates between 10 and 20 GSPS. At typical clock rates—1 GHz for the AI Engine and 500 MHz for PL—channelizers require Super Sample Rate (SSR) operation. Several I/O samples are produced and consumed on every clock cycle. A feasible clocking strategy is based on the following:
IFFT processing employs sizes N = 2^m and hardware solutions become overly complex unless SSR = 2^n. Here SSR = 4, 8, or 16 makes sense given M = 16 for this design.
Hardware design is further simplified when the input sampling rate Fs contains a factor of Q=7 matching its output oversampling factor P/Q = 8/7 because the output sampling rate is then an integral number of clock cycles.
AI Engine supports clock rates ranging from Fc = 1.0 GHz to 1.3 GHz depending on speed grade. It follows SSR = Fs/Fc ranges from 10/1.3 to 20/1.0.
A suitable clocking strategy can be identified based on these considerations. This tutorial targets a nominal Fs = 10 GSPS with SSR = 8 for an AI Engine nominal clock rate of Fc = 1.25 GHz. This performance may be met with a “-2M” speed grade device, the specific clock rates chosen as appropriate to satisfy the Q=7 divisibility requirement.