Clock Connections - Clock Connections - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English

The first connection you creat connects the SYS_CLK1_IN_0_1 port (created at the beginning of the dr.bd.tcl script) to the SYS_CLK0_IN input port of the Simulation Clock and Reset Generator IP.

Connect the SYS_CLK0 pin of the Simulation Clock and Reset Generator IP to the sys_clk0 pin of the NoC.