Multirate design is a subject explored in another section of this tutorial. This subsection emphasizes the fact that in case of different buffer sizes for destinations, the aiecompiler is able to compute a number of runs per iteration for each kernel so that the data generated by the maker is consumed by all the takers.
The architecture is exactly the same but the repetition counts are different from case 1:
Type make CASE=2 clean data aie aieviz and explore the graph view and the array view shown by the AMD Vitis™ Analyzer.
At the end of the simulation the simulator displays the throughput of the system for every port:
--------------------------------------------------------------------------------------------------
Port Name | Type | Average Throughput
--------------------------------------------------------------------------------------------------
Inputb | IN | 1250.344637 MBps
Outputb_0 | OUT | 1250.610650 MBps
Outputb_1 | OUT | 1250.814332 MBps
--------------------------------------------------------------------------------------------------
Here also the system is single rate, the only difference between the cores are the input and output buffer sizes.