CIPS Clocks - CIPS Clocks - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English

The last set of connections connects the CIPS clock pins to the NoC clock pins. A summary table of the connections is as follows:

NoC Interface

Category

NoC Clock

Connection Interface

CIPS Clock

M00_AXI

PL

aclk5

axi_dbg_hub_0/S_AXI

M01_AXI

AI Engine

aclk9

ai_engine_0/S00_AXI

S00_AXI

PS CCI

aclk0

ps_cips/FPD_CCI_NOC_0

fpd_cci_noc_axi0_clk

S01_AXI

PS CCI

aclk1

ps_cips/FPD_CCI_NOC_1

fpd_cci_noc_axi1_clk

S02_AXI

PS CCI

aclk2

ps_cips/FPD_CCI_NOC_2

fpd_cci_noc_axi2_clk

S03_AXI

PS CCI

aclk3

ps_cips/FPD_CCI_NOC_3

fpd_cci_noc_axi3_clk

S04_AXI

PS PMC

None

ps_cips/PMC_NOC_AXI_0

S05_AXI

PS NCI

aclk6

ps_cips/FPD_AXI_NOC_0

fpd_axi_noc_axi0_clk

S06_AXI

PS NCI

aclk8

ps_cips/FPD_AXI_NOC_1

fpd_axi_noc_axi1_clk

S07_AXI

PS RPU

aclk7

ps_cips/FPD_LPD_AXI_0

lpd_axi_noc_clk