Build the Contrived Design - Build the Contrived Design - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English
$ cd ../../contrived
$ make all | tee build.log

Note that the DUT and reference results match.

Use the Vitis Analyzer to examine the placement of the kernels in the AIE tile array (Figure 16).

$ vitis_analyzer Emulation-HW/aiesimulator_output/default.aierun_summary

Contrived Task Kernels in the AIE Tile Array Figure 16: Contrived Task Kernels in the AIE Tile Array

Note that the k_mtxvec and k_sumdiff kernels share a cascade stream connection (highlighted in the figure) and hence you must place them adjacent to each other.

In the Vitis Analyzer, double-click on “Graph” in the Analysis pane to view the connections between kernels (Figure 17).

Figure 17: Contrived task graph Figure 17: Contrived Task Graph

Open the trace view and check whether the matrix multipliers start roughly at the same time (Figure 18).

Contrived Task Matrix Multiplier Kernels Trace Figure 18: Contrived Task Matrix Multiplier Kernels Trace