Buffer-based AI Engine Kernels - Buffer-based AI Engine Kernels - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English

This example shows you how to construct a graph with packet switching capability. In the first section, Construct Graph with Packet Switching Capability, the example graph features:

  • Four parallel AI Engine kernels, with all four kernels sharing the same input and output ports to the PL.

  • AI Engine kernels using buffer interfaces, which means they are agnostic about how data is communicated to the PL.

This section introduces two new templated node classes, pktsplit<n> and pktmerge<n>, to construct the graph. These classes switch the packet to the correct destination and construct the packet with the corresponding packet IDs, respectively.

Then this example:

  • Introduces the Packet Format and how to Prepare Data and Run AI Engine Simulator.

  • Introduces a system design that includes Example PL Kernels for Packet Switching. In the example PL kernels, you can see how a packet is constructed and how the packet ID generated by the AI Engine compiler is used.

  • Shows PS code for the system design in Example PS code for Packet Switching.

  • Shows how to Run Hardware Emulation and Hardware flows.