Buffer Descriptor parameters - 2025.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2025-08-25
Version
2025.1 English

The goal of this section is just to show you the main registers that compose a buffer descriptor, it’s not a full training on BD programming. The documents for a complete register description for AI Engine and AI Engine-ML are the following:

For this tutorial we will concentrate on the AI Engine-ML device family.

The address generator sees the data as 1 to 3 or 4 dimension data set. For each dimension these registers define stride and wrap values. The address generator starts at some initial value and then iterates using (stride, wrap) pairs, up to a certain number of address generated. For example for a 2D data set the values stride(0), wrap(0) and stride(1) are defined. The value wrap(1) does not need to be specified as the total number of address generated is defined by the transfer length. Each of these registers are specified on a certain number of bits: