Block Design: interp1() - Block Design: interp1() - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English

The following figure shows details of the interp1() block.

  • The interp1() graph performs linear interpolation on the real (or imaginary) part of the ifft() output using the slope and offset LUTs produced by that graph. The dR_comp() graph produces the x-axis inputs at which the interpolation is performed. The SAR BP engine requires two instances of this block.

  • This block is hand-coded in AIE API but most of the code is from the Vitis DSP Library (func_approx() IP). Hand-coding means the input buffering of the slope and offset LUTs can be asynchronous. Currently, the library support is restricted to static LUT configurations, but the SAR algorithm requires new LUTs to be computed for each radar pulse.

  • The design throughput of ~430 Msps exceeds the design target of 400 Msps.

figure