Block Design: interp1() - 2025.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2025-08-25
Version
2025.1 English

Details of the interp1() block are shown in the following figure.

  • The interp1() graph performs linear interpolation on the real (or imaginary) part of the ifft() output using the slope and offset LUTs produced by that graph. The dR_comp() graph produces the x-axis inputs at which the interpolation is performed. The SAR BP engine requires two instances of this block.

  • This block is hand-coded in AIE API but the lion share of the code is harvested from the Vitis DSP Library from the func_approx() IP. Hand-coding is used so the input buffering of the slope and offset LUTs can be made asynchronous. Currently, the library support is restricted to static LUT configurations but the SAR algorithm requires new LUTs to be computed for each radar pulse.

  • The design throughput of ~430 Msps exceeds the design target of 400 Msps.

figure