Every cycle, the specified filter consumes a single pair of ‘data’ (cint16
) and ‘delay’ (int16
) input samples and produces a cint16
output sample. This can be achieved with three PLIOs connected to a single tile using streams or buffers. Even though the variable fractional delay parameter $u(nT_s)$ is specified to be int16
, each PLIO delivers 32-bits per clock cycle.
For this reason, the needed int16
value is sign extended to int32
while the sample gets delivered to the tile, then drops to int16
again during compute. Alternatively, two int16
delay samples can be packed into a single int32
sample.