Version: Vitis 2025.2
This tutorial introduces you on design partitioning into AIE-ML device. By various performance analysis techniques introduced, the design is optimized. The performance is also verified in hardware in each optimization step.
IMPORTANT: Before beginning the tutorial make sure you have installed the Vitis software platform 2025.2. The AMD Vitis™ release includes all the embedded base platforms including the VEK280 base platform that this tutorial uses. Also, make sure that you have downloaded the Common Images for Embedded Vitis Platforms from this link.
The Common Image package includes a prebuilt Linux kernel and root file system for AMD Versal boards, supporting embedded development with Vitis tools.
Before starting this tutorial, run the following steps:
Go to the directory where you have unzipped the Versal Common Image package.
In a Bash shell, run the
/**Common Images Dir**/xilinx-versal-common-v2025.2/environment-setup-cortexa72-cortexa53-amd-linuxscript. This script sets up the SDKTARGETSYSROOT and CXX variables. If the script is not present, you must run the/**Common Images Dir**/xilinx-versal-common-v2025.2/sdk.sh.Set up your ROOTFS and IMAGE to point to the
rootfs.ext4and Image files located in the/**Common Images Dir**/xilinx-versal-common-v2025.2directory.Set up your PLATFORM_REPO_PATHS environment variable to
$XILINX_VITIS/base_platforms.
This tutorial targets VEK280 board for 2025.2 version.