To realize advantages of AI Engine processing, you must vectorize computations. Applying this to pixel interpolation, the calculation can be restated as:
and
for the first two interpolations in the x coordinate, and
for the final interpolation in the y coordinate. By reformulating the computation in this way, the first two terms in each equation represent a multiply-accumulate (MAC) operation. You can use this in a follow-on multiply and subtract from accumulator (MSC) operation to obtain the result. Each interpolated pixel requires 3 MAC plus 3 MSC operations.
This example uses single precision floating-point for computation. Figure 5 shows the floating-point vector unit of an AI Engine. Observe that the multiply and accumulator units process eight lanes in parallel. SIMD parallelism uses a pixel-per-lane approach. Because each pixel requires 3 MAC plus 3 MSC operations, each of which may execute in a single clock cycle, a lower limit on computation requirement would be 0.75 cycles per pixel. Consider this bound on computation as a ballpark estimate on expected performance, which is likely unachievable due to overhead, bandwidth limitations, and pipelining inefficiencies.
Figure 5 - Floating-Point Vector Unit