AI Engine Architecture Details - AI Engine Architecture Details - 2025.2 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-03-27
Version
2025.2 English

AMD Versal™ adaptive SoCs combine programmable logic (PL), processing system (PS), and AI Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. A host of tools, software, libraries, IP, middleware, and frameworks enable Versal adaptive SoCs to support all industry-standard design flows.

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The following figure shows an AI Engine array:

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As you can see in the preceding image, each AI Engine is connected to four memory modules on the four cardinal directions. The AI Engine and memory modules are both connected to the AXI-Stream interconnect.

The AI Engine is a VLIW (7-way) processor that contains:

  • Instruction Fetch and Decode Unit

  • A Scalar Unit

  • A Vector Unit (SIMD)

  • Three Address Generator Units

  • Memory and Stream Interface

The following figure shows an AI Engine module:

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Look at the fixed-point unit pipeline and floating-point unit pipeline within the vector unit.