32x32 Matrix Multiplication Latency - 32x32 Matrix Multiplication Latency - 2026.1 English - XD100

Vitis Tutorials: AI Engine Development (XD100)

Document ID
XD100
Release Date
2026-06-23
Version
2026.1 English

For the first 32 clocks, Matrix A Row 0 is loaded into first cascade chain. Over next 32 clocks, First cascade chain calculates first row of output matrix, and for next 32 clocks, other rows of output matrix are generated. However after 64 clocks, first DSP cascade chain can receive first row data for next 32x32 matrix.

Larger matrices are reduced to smaller 32x32 matrices. For example, 1Kx1Kx1K matrices are represented as follows, where each box is 32x32 matrix.

Image of GEMM DSP Implementation Submatrices

The following figure shows the output matrix.

Image of GEMM DSP Implementation Output Matrix