This section lists the registers available in the DisplayPort 2.1 RX Subsystem. The address map is split into the following regions:
- DisplayPort RX IP
- AXI IIC
- HDCP Controller
- AXI Timer
The following table shows the address offsets of the helper cores.
| Helper Core | Address Space | Address Offset |
|---|---|---|
| DisplayPort | 8K | 0x0000_0000 |
| AXI IIC | 4K | 0x0000_2000 |
| AXI Timer | 4K | 0x0000_3000 |
| HDCP 1.x Subsystem | 4K | 0x0000_4000 |
| HDCP 2.x Subsystem | 16K | 0x0000_8000 |
The subsystem address propagation in the AMD Vivado™
IP integrator assigns the maximum addresses based on
full-featured configuration. Ensure the following:
- Confirm that the DisplayPort 2.1 RX Subsystem IP is mapped to a base address where the 14th bit in the
address is 0. For example,
0x44A00000is correct, and0x44A02000causes errors. - Ensure all 14 bits of the address range are reserved for the DisplayPort 2.1 RX Subsystem IP.