| Offset | Access Type | Description |
|---|---|---|
| 0x500 | RO | MSA_HRES. The horizontal resolution detected in the Main Stream
Attributes. [15:0] - Represents the number of pixels in a line of video |
| 0x504 | RO | MSA_HSPOL. Horizontal sync polarity. [0] - Indicates the polarity of the horizontal sync as requested by the transmitter |
| 0x508 | RO | MSA_HSWIDTH. Specifies the width of the horizontal sync
pulse. [14:0] - Specifies the width of the horizontal sync in terms of the recovered video clock |
| 0x50C | RO | MSA_HSTART. This main stream attribute is the number of clock
cycles between the leading edge of the horizontal sync and the first cycle of active
data. [15:0] - Number of blanking cycles before active data |
| 0x510 | RO | MSA_HTOTAL. Tells the receiver core how many video clock cycles
occur between leading edges of the horizontal sync pulse. [15:0] - Total number of video clocks in a line of data |
| 0x514 | RO | MSA_VHEIGHT. Total number of active video lines in a frame of
video. [15:0] - Vertical resolution of the received video |
| 0x518 | RO | MSA_VSPOL. Specifies the vertical sync polarity requested by
the transmitter. [0] - A value of 1 in this register indicates an active-High vertical sync. A 0 indicates an active-Low vertical sync. |
| 0x51C | RO | MSA_VSWIDTH. The transmitter uses this value to specify the
width of the vertical sync pulse in lines. [14:0] - Specifies the number of lines between the leading and trailing edges of the vertical sync pulse. |
| 0x520 | RO | MSA_VSTART. This main stream attribute specifies the number of
lines between the leading edge of the vertical sync pulse and the first line of
active data. [15:0] - Number of blanking lines before the start of active data |
| 0x524 | RO |
MSA_VTOTAL. Total number of lines between sequential leading edges of the vertical sync pulse. [15:0] - Total number of lines per video frame is contained in this value |
| 0x528 | RO |
MSA_MISC0. Contains the value of the MISC0 attribute data. [7:5] - COLOR_DEPTH: Number of bits per color/component. [4] - YCbCR_COLOR: Set to 1 (ITU-R BT709-5) or 0 (ITU-R BT601-5). [3] - DYNAMIC_RANGE: Set to 1 (CEA range) or 0 (VESA range). [2:1] - COMPONENT_FORMAT:
[0] - CLOCK_MODE:
|
| 0x52C | RO | MSA_MISC1. Contains the value of the MISC1 attribute data. [7] - Implements the attribute information contained in the DisplayPort MISC1 register. See the VESA DisplayPort Standard (VESA website) section 2.2.4 for more information. [6] - Implements the attribute information contained in the DisplayPort MISC1 register. See the VESA DisplayPort Standard (VESA website) section 2.2.4 for more information. [5:3] - RESERVED: Bits are always set to 0 [2:1] - STEREO_VIDEO: Used only when stereo video sources are being transmitted. See the VESA DisplayPort Standard (VESA website) section 2.2.4 for more information. [0] - INTERLACED_EVEN: 1 indicates that the number of lines per frame is an even number |
| 0x530 | RO |
MSA_MVID. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_NVID registers. [23:0] - MVID: Value of the clock recovery M value. |
| 0x534 | RO |
MSA_NVID. This attribute value is used to recover the video clock from the link clock. The recovered clock frequency depends on this value as well as the CLOCK_MODE and MSA_MVID registers. [23:0] - NVID: Value of the clock recovery N value. |
| 0x538 | RO |
MSA_VBID. The most recently received VB-ID value is contained in this register. [7:0] - VBID: See Table 2-3 (pg. 44) in the VESA DisplayPort Standard (VESA website) for more information. The default value is 0x19. |
| 0x540 to 0x578 | RO | Bit definition is identical to that of the MSA Values registers (0x500 to 0x538), but for MST STREAM 2. |
| 0x580 to 0x5B8 | RO | Bit definition is identical to that of the MSA Values registers (0x500 to 0x538), but for MST STREAM 3. |
| 0x5C0 to 0x5F8 | RO | Bit definition is identical to that of the MSA Values registers (0x500 to 0x538), but for MST STREAM 4. |
| 0x1608 | RO |
VFREQ[23:0] - When [1:0] of 0x434 is 0x10 (that is, for 128b/132b), The VFREQ field holds the lower 24bits [23:0] of absolute pixel rate in units of Hz within ±1% accuracy. When [1:0] of 0x434 is 0x01 (for 8b/10b), this field is invalid [23:0] - [23:0] bits of VFREQ value |
| 0x160C | RO |
VFREQ[47:24] - When [1:0] of 0x434 is 0x10 (that is, for 128b/132b), The VFREQ field holds the upper 24bits [47:24] of absolute pixel rate in units of Hz within ±1% accuracy. When [1:0] of 0x434 is 0x01 (that is, for 8b/10b), this field is invalid [23:0] - [47:24] bits of VFREQ value |
| 0x1610 | RW | Same as 0x1608 and 0x160C but for MST STREAM 2. |
| 0x1614 | ||
| 0x1618 | RW | Same as 0x1608 and 0x160C but for MST STREAM 3. |
| 0x161C | ||
| 0x1620 | RW | Same as 0x1608 and 0x160C but for MST STREAM 4. |
| 0x1624 | ||
| 0x1628 | RW | The AFREQ field carries the rate (in Hz) of the absolute
primary audio clock. A DP Source device AFREQ value needs to be set within the ±1%
accuracy. [23:0] - [23:0] bits of AFREQ value. Only applicable for 128b132b link rates. |
| 0x162C | RW | The AFREQ field carries the rate (in Hz) of the absolute
primary audio clock. A DP Source device AFREQ value needs to be set within the ±1%
accuracy. [23:0] - [47:24] bits of AFREQ value. Only applicable for 128b132b link rates. |