|
Subsystem Specifics |
| Supported Device Family
1
|
AMD UltraScale+™
Families (GTHE4, GTYE4)
4
|
| Supported User Interfaces |
AXI4-Stream, AXI4-Lite, Native video |
| Resources |
Performance and Resource Use
Webpage
|
| Provided with Subsystem
|
| Design Files |
Hierarchical subsystem packaged with DisplayPort RX core and other IP cores |
| Example Design |
AMD Vivado™
IP
integrator |
| Test Bench |
Not provided |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Not provided |
| Supported S/W Driver |
Standalone
|
| Tested Design Flows
3
|
| Design Entry |
Vivado Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 36990
|
| All Vivado IP Change
Logs |
Master Vivado IP Change
Logs: 72775
|
|
Support web
page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- Standalone driver details can be found in the
directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).
Linux OS and driver support
information is available from the
Wiki page
- For the supported versions of third-party
tools, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
- For families
supporting GTHE4, the Link Rate selection is supported only up to 13.5 Gb/s and for families
supporting GTYE4, the Link Rate selection is supported till 20 Gb/s.
|