Address Map Example - 1.0 English - PG422

DisplayPort 2.1 RX Subsystem Product Guide (PG422)

Document ID
PG422
Release Date
2025-11-26
Version
1.0 English

The following table shows an example based on a subsystem base address of 0x44A0_0000 (14 bits). There are no registers in the Video to AXI4-Stream bridge.

Table 1. Address Map Example
IP Core/Subsystem SST MST
DisplayPort 2.1 RX 0x44A0_0000 0x44A0_0000
AXI IIC Controller 0x44A0_2000 0x44A0_2000
AXI Timer 0x44A0_3000 0x44A0_3000
HDCP 1.3 Controller 0x44A0_4000 0x44A0_4000
HDCP 2.3 Controller 0x44A0_8000 0x44A0_8000