AXI Timer IP Core - 1.0 English - PG422

DisplayPort 2.1 RX Subsystem Product Guide (PG422)

Document ID
PG422
Release Date
2025-11-26
Version
1.0 English

A 32-bit AXI Timer IP core is used in the DisplayPort 2.1 RX Subsystem. The AXI Timer can be accessed through the AXI4 master interface for basic timer functionality in the system.