Versal Adaptive SoC Hard Block Ports - Versal Adaptive SoC Hard Block Ports

Versal Adaptive SoC Hard Block Ports - Versal Adaptive SoC Hard Block Ports - PG457

800G IEEE 802.3df Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG457)

Document ID

PG457

Release Date

2025-11-20

Revision

1.0 English

The following clock ports are present on the core to support the use of the FEC functionality within the DCMAC.

Table 1. Versal Adaptive SoC Hard Block Ports
Port	I/O	Clock	Description
apb3_clk	I	N/A	Required by the DCMAC Subsystem. Must be continuously present for correct operation.
rx_port<N>_clk_x2	I	N/A	Double-rate clock for transmit side. This clock must run at exactly twice the frequency of the rx_port<N>_serdes0_clk input. Take care to minimize any variation in the relative phase of this pair of clocks.
tx_port<N>_clk_x2	I	N/A	Double-rate clock for receive side. This clock must run at exactly twice the frequency of the tx_port<N>_clk input. Take care to minimize any variation in the relative phase of this pair of clocks.