The following table shows the user signals at the top level of the design.
| Port Name | Bit width | Direction | Description |
|---|---|---|---|
| init_clk | 1 | I | 100 MHz system clock |
| tx_clk | 1 | I | 332.03125 MHz transmit clock for the TX SERDES interface |
| rx_clk | 1 | I | 332.03125 MHz receive clock for the RX SERDES interface |
| apb3_clk | 1 | I | 100-300 MHz clock needed for DCMAC configuration. |
| tx_clk_x2 | 1 | I | 664.0625 MHz double rate transmit clock for DCMAC |
| rx_clk_x2 | 1 | I | 664.0625 MHz double rate receive clock for DCMAC |
| sys_reset | 1 | I | System reset. Resets all the modules in the Example Design and the TX and RX resets in the IP. |
| tx_port<N>_done_led | 1 | O | Indicates the transmitter has sent 24 frames to a port |
| tx_port<N>_fail_led | 1 | O | Reserved. Always set to zero. |
| tx_port<N>_busy_led | 1 | O | Indicates out of reset. Data will be sent immediately after reset. |
| rx_port<N>_aligned_led | 1 | O | Indicates that RX alignment has been achieved for that port. |
| rx_port<N>_done_led | 1 | O | Indicates that the monitor has received all packets for a port. |
| rx_port<N>_data_fail_led | 1 | O | Indicates data comparison failed in the packet monitor for that port. |
| rx_port<N>_busy_led | 1 | O | Indicates the monitor is checking correct data for that port. |
| rx_port<N>_uncorrected_led | 1 | O | Indicates that one of the two codewords was uncorrectable for the port. |
| rx_port<N>_corrected_led | 1 | O | Indicates that a correctable error has been observed for the port. |
| rx_port<N>_cw_inc_led | 1 | O | Indicates a codeword has been processed by the decoder for that port |
| init_heartbeat | 1 | O | Indicates that the 100 MHz init clock is running |