The data on the SerDes interfaces on the RX and TX interfaces is arranged into 32 lanes of 80 bits each. The bit ordering within each lane is right to left, such that bit 0 represents the first bit transmitted (or received) and bit 79 represents the last bit transmitted (or received).
Further external re-ordering/interleaving might be required to connect the core to the SerDes block according to the details of the transceiver implementation.
IEEE 802.3df-2024 Clause 173 specifies how bits from multiple PCS lanes are interleaved for transmission to form one physical lane. It also specifies how a stream of bits received on one physical lane must be de-interleaved to form multiple PCS lanes prior to alignment and FEC decoding.
There is no flow control on the SerDes interfaces; data is transmitted (or received) on every cycle. The data rate is 80 bits per cycle per lane, equating to 32 x 80b x 332.03125 MHz = 850 Gb/s.
On the RX SerDes interface, static inter-lane skew of up to 152 ns and dynamic inter-lane skew variation of up to 4 ns is supported according to the IEEE standard.