The core has a total of nine resets, one per clock domain (except that there is no reset associated with the additional DCMAC clocks).
All resets are active-Low. During configuration, these resets need to be asserted Low and only after the clocks are stable, the resets should be released.
The reset procedure is simple and the only requirement is that a reset must be asserted until the corresponding clock(s) are stable. The core ensures that the different resets are properly synchronized to the required domain.
The resets must be held for a minimum of 24 ns or 8 × the cycle time of the associated clock inside the DCMAC. For example, rx_port<N>_serdes{0:7}_resetn must be held for 8 × rx_port<N>_clk_x2 cycles. The same applies to tx_port<N>_resetn and tx_port<N>_clk_x2.
During normal operation for the RX and TX paths, the resets can be asserted independently.