PCS Data Per Flow - PCS Data Per Flow - PG457

The data buses on the RX and TX PCS interfaces are 1285 bits wide. This number (which is 5 x 257) is chosen to be convenient for the alignment marker insertion/removal and transcoding logic in the PCS block, because these functions operate on 257-bit blocks. The block ordering within these buses is from right to left, such that bits 256:0 represent the first 257-bit block, bits 513:257 represent the second block, bits 770:514 the third, bits 1027:771 the fourth, and bits 1284:1028 the fifth.

The bit ordering within each block is also from right to left, such that bit 0 is the first bit of the first block and bit 1284 is the last bit of the last block. Flow control on the PCS interface is by means of a data-valid signal in each direction. Under normal circumstances, data transfer occurs on 16 out of every 17 clock cycles.

Figure 1. Timing Diagram