The following figures shows the module hierarchy instantiated at the top level of the example design. The <CN> designator in the figure is replaced by the component name of the generated RS-FEC core instance. The <CN>_800g module contains:
- Reset controller to manage reset and initialization of the example design
- Data packet generator and monitor
- Error insertion module
- Statistics module
- Degraded SER Analyzer
The data loopback occurs at the end of the transmit register pipeline
on the SERDES interface.
The PCS stimulus generator starts sending packets immediately after reset is released, taking advantage of internal buffers. The correct behavior is checked by the PCS checker module, which compares received packets against a common update function to see if they match what was sent by the stimulus generator.
After alignment is achieved on a given port, correctable errors higher than the degrade activation threshold are injected. The console prints messages informing you that the Degraded SER Analyzer has detected errors higher than the degrade activation threshold. The Error Generator then stops injecting errors to drive the count below the degrade deactivation threshold, and the console logs that errors are below this threshold. Similarly, messages are printed in the console informing you that the number of errors is lower than the degrade deactivation threshold. To disable degradation, disable the DEGRADE_TESTING define in the example design test bench. With degradation disabled, no errors are injected into the IP.
The following figure shows the expected order of the virtual LED outputs. The
timing diagram is not clock cycle-accurate; expect about 45 minutes of simulation
before the message Test Completed Successfully for port
<N> is reported. The tx_port<N>fail_led is wired to 0 because it is a reserved
signal, and it does not toggle. However, if the rx_port<N>_data_fail_led is asserted, the PCS data differs from
Packet Received Monitor expectations.
The following figure shows the datapath signals. By default, tx_port<N>_resetn deasserts on the cycle when
tx_port<N>_pcs_data_flow<N> has
valid data. This adds delay beyond the TX delay before tx_port<N>_serdes_data_out is available. However, you can choose
to release the tx_port<N>_resetn earlier in
the simulation by changing the FEC_RESET_LIMIT parameter to the number of clock
cycles that you want to delay the tx_reset in
<CN>_800g.v.