Design Flow Steps - Design Flow Steps - PG457

800G IEEE 802.3df Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG457)

Document ID
PG457
Release Date
2025-11-20
Revision
1.0 English

This section describes customizing and generating the core, constraining the core, and the simulation, synthesis, and implementation steps that are specific to this IP core. More detailed information about the standard AMD Vivado™ design flow can be found in the following Vivado Design Suite user guides:

  • Vivado Design Suite User Guide: Designing with IP (UG896)
  • Vivado Design Suite User Guide: Getting Started (UG910)
  • Vivado Design Suite User Guide: Logic Simulation (UG900)