The 800G RS-FEC core implements the Reed-Solomon Forward Error Correction (RS-FEC) functions, which are part of the 800GBASE-R PCS layer, as described in IEEE 802.3df and shown shaded in the following figure.
Figure 1. Architectural Position of 800G Ethernet PCS Layer
The 800G RS-FEC core provides FEC encoding and decoding functionality using the hard RS-FEC encoding and decoding functionality within the DCMAC hard blocks. This helps reduce FPGA fabric resources and allows efficient sharing of DCMAC resources across up to three 800G ports.
Note: DCMAC hard blocks used for encoding and decoding
cannot be used in parallel for other Ethernet functions.