| rx_port<N>_am_period[15:0] |
I |
rx_port<N>_serdes0_clk |
Frame length (period between AMs), in number of codeword
pairs |
| rx_port<N>_stat_align_status |
O |
rx_port<N>_serdes0_clk |
Overall RX align/deskew status |
| rx_port<N>_lane_locked[31:0] |
O |
rx_port<N>_serdes0_clk |
Per-PCS lane AM lock status |
| rx_port<N>_lane_delay[511:0] |
O |
rx_port<N>_serdes0_clk |
Per-lane deskew delay report (UIs). Each lane has a 16 bit
delay value. The MSB 16 bit of this signal represent the delay of lane 31 and so on
in descending order, that means LSB 16 bit is lane 0. The 16 bit delay number for
each lane contains the word delay and the bit shift, so the delay for lane 0 can be
calculated as: (rx_port<N>_delay[15:8]]+1-rx_port<N>_delay[6:0]/80) x
clock_period. |
| rx_port<N>_lane_mapping[159:0] |
O |
rx_port<N>_serdes0_clk |
Lane mapping detected. 5 bit number per lane where the lanes
are in descending order, for example, rx_port_lane_mapping[4:0] is the lane mapping
of lane 0. |
| rx_port<N>_stat_cw_inc_flow0[1:0] |
O |
rx_port<N>_serdes0_clk |
Total CW count increment for flow 0 |
| rx_port<N>_stat_cw_inc_flow1[1:0] |
O |
rx_port<N>_serdes0_clk |
Total CW count increment for flow 1 |
| rx_port<N>_stat_cw_inc_port[2:0] |
O |
rx_port<N>_serdes0_clk |
Total CW count increment per port |
| rx_port<N>_stat_corrected_cw_inc_flow0[1:0] |
O |
rx_port<N>_serdes0_clk |
Corrected CW count increment for flow 0 |
| rx_port<N>_stat_corrected_cw_inc_flow1[1:0] |
O |
rx_port<N>_serdes0_clk |
Corrected CW count increment for flow 1 |
| rx_port<N>_stat_corrected_cw_inc_port[2:0] |
O |
rx_port<N>_serdes0_clk |
Corrected CW count increment per port |
| rx_port<N>_stat_uncorrected_cw_inc_flow0[1:0] |
O |
rx_port<N>_serdes0_clk |
Uncorrected CW count increment for flow 0 |
| rx_port<N>_stat_uncorrected_cw_inc_flow1[1:0] |
O |
rx_port<N>_serdes0_clk |
Uncorrected CW count increment for flow 1 |
| rx_port<N>_stat_uncorrected_cw_inc_port[2:0] |
O |
rx_port<N>_serdes0_clk |
Uncorrected CW count increment per port |
| rx_port<N>_stat_cw_error_count_inc_flow0[9:0] |
O |
rx_port<N>_serdes0_clk |
CWA(bits[9:5]) and CWB (bits[4:0]) error count increment for
flow 0 |
| rx_port<N>_stat_cw_error_count_inc_flow1[9:0] |
O |
rx_port<N>_serdes0_clk |
CWA(bits[9:5]) and CWB (bits[4:0]) error count increment for flow 1 |
| rx_port<N>_stat_lane_error_inc[159:0] |
O |
rx_port<N>_serdes0_clk |
Per-lane error count increment. 5 bit number per lane where
the lanes are in descending order, for example, rx_port<N>_stat_lane_error_inc
[4:0] is the lane error count of lane 0. |
| rx_port<N>_stat_degraded_ser_flow0 |
O |
rx_port<N>_serdes0_clk |
Degraded-SER status for flow 0 |
| rx_port<N>_stat_degraded_ser_flow1 |
O |
rx_port<N>_serdes0_clk |
Degraded-SER status for flow 1 |
| rx_port<N>_stat_degraded_ser_port |
O |
rx_port<N>_serdes0_clk |
Degraded-SER status per port |
| rx_degrade_enable |
I |
rx_port<N>_serdes0_clk |
Enable degraded-SER monitoring |
| rx_degrade_act_thresh[31:0] |
I |
rx_port<N>_serdes0_clk |
Activation threshold for degraded-SER monitoring |
| rx_degrade_deact_thresh[31:0] |
I |
rx_port<N>_serdes0_clk |
Deactivation threshold for degraded-SER monitoring |
| rx_degrade_interval[31:0] |
I |
rx_port<N>_serdes0_clk |
Measurement interval for degraded-SER monitoring (in CW pairs)
|