Constraining the Core - Constraining the Core - PG457

800G IEEE 802.3df Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG457)

Document ID
PG457
Release Date
2025-11-20
Revision
1.0 English

Device, Package, and Speed Grade Selections

For Versal Premium devices that have widely separated DCMAC instances, it might be necessary to apply additional floor planning and/or placement constraints to meet the timing requirement. This core supports only -2M, -2H and -3 speed grades.

Clock Frequencies

This section is not applicable for this IP core.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.