The 800G RS-FEC core has 11 clocks per
port and three clocks shared between ports. There is one clock for the transmit path, tx_port<N>_clk, and eight clocks for the receive path,
rx_port<N>_serdes{0-7}_clk. There is also a
free-running clock for the DCMAC's APB3 interface, apb3_clk,
a double-rate clock for RX processing, rx_port<N>_clk_x2, and a double-rate clock for TX processing, tx_port<N>_clk_x2. Additionally, the DCMAC's internal logic
operation requires rx_axi_clk and core_clk_x2.
- Receive GT/Lane logic clock (rx_port<N>_serdes{0-7}_clk)
- These eight clocks are the recovered clocks from the receive transceivers. They must all have the same underlying frequency but can vary dynamically in phase. Some or all of the eight clocks can share the same source, that is, there can be between 1 and 8 distinct receiver input clock domains. The lane 0 clock is treated as the primary clock, and the data from all other lanes is brought into the lane 0 domain by a CDC FIFO within the IP. The RX transceiver lane 0 clock is also used to clock the receive datapath so that the required throughput is maintained on the receive path. The signaling rate per PCS lane must be 26.5625 Gb/s ±100 ppm. The clock rate for the SerDes clocks is therefore nominally, 332.03125 MHz.
- Transmit clock (tx_port<N>_clk)
- This clock is provided to the core’s transmit datapath. Its frequency must be 332.03125 MHz to achieve a signaling rate of 26.5625 Gb/s per PCS lane.
- APB3 clock (apb3_clk)
- DCMAC requires this clock for correct operation. Its frequency must be between 100-300 MHz.
- Double-rate transmit clock (tx_port<N>_clk_x2)
- DCMAC blocks are provided with this clock. Its frequency must be exactly
double that of
tx_port<N>_clk(nominally, 664.0625 MHz). Ensure to minimize any phase variation between this pair of clocks. Ideally, they must be generated from the same PLL. - Double-rate receive clock (rx_port<N>_clk_x2)
- DCMAC blocks are provided with this clock. Its frequency must be
exactly double that of
rx_port<N>_serdes0_clk(nominally, 664.0625 MHz). Ensure to minimize any phase variation between this pair of clocks. Ideally, they must be generated from the same PLL. - AXI receive clock (rx_axi_clk)
- DCMAC requires this clock for correct operation. It can run at a nominal frequency of 195.3125 to 390.625 MHz.
- Core clock (core_clk_x2)
- DCMAC requires this clock to have a frequency exactly double that of
rx_port<N>_serdes0_clk(nominally, 664.0625 MHz) and is required for operation of datapath logic within the DCMAC.