Clock and Reset Ports - Clock and Reset Ports - PG457

800G IEEE 802.3df Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG457)
Document ID
PG457
Release Date
2025-11-20
Revision
1.0 English
Table 1. Clock and Reset Ports
Port Name I/O Clock Description
rx_axi_clk I N/A Must be present for the DCMAC Subsystem to function
core_clk_x2 I N/A Used in the DCMAC Subsystem to drive internal logic. If this clock is interrupted, the DCMAC Subsystem enters an error state.
rx_port<N>_serdes{0:7}_clk I N/A Nominal frequency clocks for the transceiver interface. Used for the data transmission in the RX path. rx_port<N>_serdes0_clk is the primary clock for all the RX datapath logic.
tx_port<N>_clk I N/A Nominal frequency clocks for the transceiver interface. Used for the data transmission in the TX path.
tx_port<N>_resetn I tx_port<N>_clk Transmit reset (active-Low)
rx_port<N>_serdes{0:7}_resetn I rx_serdes{0:7}_clk Receive resets (active-Low)