76893 - Versal: JTAG TDO - 76889 is a Design Advisory for Versal ACAPs which details the MIO and HDIO requirements when tristate control is changing. This Article discusses the JTAG TDO use case. If VCCO_503 is 3.3V or 2.5V, then JTAG TDO_503 can be affected by the tristate data race condition. As a result, TDO output can fail to drive Programmable Logic (PL) ‘1’ LSB bit values. The Processing Subsystem (PS) Arm DAP and PL BYPASS data output features are not affected by this issue.

Release Date

2023-03-09

Revision

1.0 English