76889 - Versal HDIO/MIO: When powered at 3.3V or 2.5V a race condition can exist between data and tristate

Release Date

Violating the skew requirement can lead to a race condition causing incorrect logic levels. The affected pad remains at the stuck value until I or T is toggled again. This minimum skew requirement does not apply when the banks are powered at 1.8V.

Please refer to the flowcharts below to assess if a design is affected:


HDIO usage:


MIO usage:
JTAG TDO usage:


Details on the skew requirement and specific work-around for each use case can be found in the relevant answer record below.

1. HDIO – OBUFT, IOBUFT76846 - Versal: HDIO OBUFT and IOBUF Tristate timing implications
2. Sysmon I2C/PMBus usage76890 - Versal: Sysmon I2C/PMBus usage
3. MIO SelectMAP Interfaces76891 - Versal: MIO SelectMAP Interfaces
4. MIO USB2.0 Interfaces76892 - Versal: MIO USB 2.0 Interfaces
5. JTAG TDO76893 - Versal: JTAG TDO
6. JTAG HDIO and MIO EXTEST76894 - Versal: JTAG EXTEST with PS MIO and PL HDIO at 3.3V or 2.5V
7. GTS assertion76914 - Versal: Global Tristate (GTS) with PL HDIO at 3.3V or 2.5V
8. SRST assertion76914-1 - Versal: System Reset (SRST) considerations when HDIO is powered at 2.5V/3.3V

Impacted Devices : All package and speed grade combinations of VC1902, VC1802, VM1802, VM1302, VM1402 and these ES1 devices: VP1202, VP1502, VP1552, VP1702, VP1802, VH1522, VH1542 and VH1582.

Revision History:
09/30/2021: Initial Release
12/15/2021: Added additional devices to Impacted Devices list. Updated Flow diagrams.