76846 - Design Advisory - Versal: HDIO OBUFT and IOBUF Tristate timing implications

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76889 - Versal HDIO/MIO: When powered at 3.3V or 2.5V, a race condition can exist between data and tristate when using a tristate is a Design Advisory for Versal Adaptive SoCs which details the MIO and HDIO requirements when tristate control is changing.


This Article discusses the HDIO OBUFT and IOBUF use case.


When an HDIO output buffer with tristate control (OBUFT/IOBUF) is powered at 3.3V or 2.5V and both the Data and Tristate control signals toggle close in time to one another, it can be affected by the tristate-data race condition.

The race condition only causes the issue when the tristate and data switch are opposite to each other (for example, tristate 0 -> 1 and Data 1 ->0). It does not cause issues when both the tristate and data switch are in the same direction (for example tristate 0 -> 1 and Data 0-> 1).

The resulting output can drive an incorrect pad voltage. The pad can be stuck at this incorrect voltage until the tristate (dataValidBeforeTristate scenario) or the data (dataValidAfterTrisate scenario) toggles again.


dataValidBeforeTristate = 550ps
dataValidAfterTristate = 200ps

Impacted Devices: VC1902, VC1802, VM1802, VM1402, VM1302 in packages other than the VSVD1760.

Only devices with HD banks are affected by the HDIO IOBUF AND OBUFT use case. The  VSVD1760 packages do not have a HDIO bank and therefore are not impacted.  


Affected IP cores:

Although the use of HDIO is often not dictated by the IP, the following IP cores are likely to use the HDIO buffer in a manner that could be impacted by this issue. The attached Tcl script can be used to help adjust the Data to Tristate route relationship in many scenarios:

• AXI 1G Ethernet
• TriMode Ethernet MAC