In designs generated for Zynq UltraScale+ MPSoC/RFSoC devices in all versions of Vivado up to and including 2024.2, you might observe link training failures or data errors on PCIe, USB3.0, or SATA protocols when using PS GTR.
In designs generated for Zynq UltraScale+ MPSoC/RFSoC devices in all versions of Vivado up to and including 2024.2, you might observe link training failures or data errors on PCIe, USB3.0, or SATA protocols when using PS GTR.