Power-On 0-1-0 Transition
The recommended power-on sequence for UltraScale Devices is VCCINT/VCCINT_IO, VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO.
When this sequence is followed, the Master SLRs I/Os will remain in 3-state during power-on.
However when PUDC_B is pulled High (disable pull-up on I/Os during configuration) I/Os located in Slave SLRs might see a 0-1-0 transition between VCCO_0 powering up and INIT_B asserting.
This assertion is a result of the I/O changing from 3-state to a weak pull-up and back to 3-state.
This assertion can last from several hundred microseconds to a few milliseconds.
Power-Off 0-1-0 Transition
The recommended power-off sequence is the reverse of power-on (VCCO, VCCAUX/VCCAUX_IO, VCCBRAM, VCCINT/VCCINT_IO) but when VCCO_0 is powered down and the device has not been configured, a 0-1-0 transition can be observed on I/Os located in a Slave SLR.
This assertion is a result of the internal weak pull-up resistor being temporarily enabled.
Work-arounds
Any 0-1-0 transition due to the enabling of the weak pull-up resistor will not impact the FPGAs functionality or its configuration sequence.
It will only impact downstream devices. For designs sensitive to 0-1-0 transitions on power-on or power-down:
1) A 1K Ohm pull-down to ground will generally be a strong enough for most applications to ensure the weak pull-up enable does not cross into the logic 1 threshold for most downstream devices.
See IRPU in the appropriate data sheet for the pull-ups strength range. See the appropriate data sheet: Kintex UltraScale and/or Virtex UltraScale
2) Ensure all downstream devices sensitive to a 0-1-0 transition are connected to I/O in the Master SLR and follow the recommended power sequence.
3) If the device can tolerate a high level, but not a glitch, PUDC_B can be pulled low to enable the pull-up throughout the sequence.
DEVICES IMPACTED:
| Device | Package | Banks that contain I/Os that might have a 0-1-0 transition |
| XCKU085 | FLVB1760 | 49,50,51,52 |
| XCKU085 | FLVF1924 | 51,52,70,71,72 |
| XCKU115 | FLVB1760 | 49,50,51,52,53 |
| XCKU115 | FLVD1924 | 50,51,52,53,70,71,72,73 |
| XCKU115 | FLVF1924 | 51,52,53,70,71,72,73 |
| XCKU115 | FLVA2104 | 50,51,52,53,70,71,72,73 |
| XCKU115 | FLVB2104 | 51,52,53,71,72,73 |
| XCVU125 | FLVD1517 | 71,72,73 |
| XCVU125 | FLVB1760 | 49,50,51,52,53 |
| XCVU125 | FLVA2104 | 50,51,52,53,70,71,72,73 |
| XCVU125 | FLVB2104 | 50,51,52,70,71,72 |
| XCVU125 | FLVC2104 | 70,71,72 |
| XCVU160 | FLVB2104 | 50,51,52,70,71,72 |
| XCVU160 | FLVC2104 | 70,71,72 |
| XCVU160 | FLGB2104 | 50,51,52,70,71,72 |
| XCVU190 | FLGC2104 | 70,71,72 |
| XCVU190 | FLGA2577 | 70,71,72,61,62,63 |
| XCVU440 | FLGB2377 | 50,51,52,53,70,71,72,73,40,41,42,43,60,61,62,63 |
| XCVU440 | FLGA2892 | 49,50,51,52,53,70,71,72,73,39,40,41,42,43,60,61,62,63 |
Note: 7 Series and UltraScale+ devices are NOT impacted by this issue.
Some of the devices above are available in packages that have no I/O banks in the slave SLR and thus will not be impacted.