Description - Description

69202 - Design Advisory for Kintex UltraScale FPGAs and Virtex UltraScale FPGAs - 3D IC devices can enable the weak pull-up on I/Os located in Slave SLRs during power-on and power-off
Release Date
2023-02-16
Revision
1.0 English

For Virtex UltraScale and Kintex UltraScale 3D ICs based on SSI technology, I/Os in a slave SLR bank might have a 0-1-0 transition.

This is caused by the enabling of the internal weak pull-up resistors during power-on and power-off under certain circumstances.